The present invention relates generally to electronic devices and circuits and, more particularly, to an improved differential integrator and related circuitry.
As electronics continue to get faster, more data is required to travel between the chips that process the data. In order to reliably transmit or receive the data, a clock signal is typically sent with the data. If only one edge of the clock signal is used for synchronizing the data, the clock signal frequency will need to be twice the frequency of the data. This doubling of clock signal frequency can easily become the system limiting factor because higher frequency signals are harder to transmit.
The clock signal can be slowed to the same frequency of the data if both edges of the clock signal are used to synchronize the data. However, this requires that both halves of the clock signal have an equal 50%/50% duty cycle, so that each piece of data has a maximum transmit or receive time. A duty cycle corrector can correct a bad clock signal by measuring the on-time and the off-time of the clock signal, and then adjusting the clock signal until the on-time and off-time are equal, thus producing an equal 50%/50% duty cycle clock signal.
The key to achieving accurate clock signal correction is an integrator. That is, an integrator is used to measure the on-time and the off-time of a clock signal, and an error signal is generated if the two are not equal. The integrator may be single-ended or differential, but in either case, as technology advances, it actually gets more difficult to make high quality integrators. This is due to several factors, including the following: voltages being reduced; devices getting smaller; some physical parameters not changing as fast as others; leakage currents; and less ideal devices. To overcome these limitations, new circuit techniques are needed to produce an integrator with small internal error. Currently, without these new circuit techniques, duty cycle errors of two percent are not uncommon, and this problem will only get worse as technology continues to advance.
For example, when using a differential integrator to generate an error voltage, a large output swing is desired to reduce jitter caused by differential noise and power supply noise. For maximum differential output range of a differential integrator, output common-mode should be at one-half the operating voltage (i.e., xc2xdVDD) to provide maximum saturation voltage for nmos and pmos current sources performing the integration. However, the generated voltage must drive a differential-pair to perform the correction for which it was established. In low voltage (i.e., less than 2 volts as measured between a transistor gate and source) applications, neither an nmos nor pmos differential-pair will operate in a dead band region centered around xc2xdVDD. Additionally, because the integrator is integrating charge, any differential charge that is output thereby directly translates into an integrating error. This means that traditional methods of level shifting fail. For example, a source-follower is differentially range limited because it is single ended, and a resistive divider causes a differential current error. As a result, an alternative is needed to achieve maximum output range.
Another problem arises when a large output swing is desired, which is especially true in low-voltage applications. A small overdrive voltage for transistors operating as current-sources requires a large transistor width/length (W/L) ratio. To save area and parasitic capacitance (e.g., speed and charge injection errors), a small L is used and only constrained by the matching desired. This now means that channel-length modulation (CLM) is the dominant source of mismatch between the differential current sources. This too must be reduced for a high-precision integrator (i.e., an integrator used to correct duty cycle error to less than two percent for all corners of operation, with that percentage of error potentially increasing as technology advances). In general, as mentioned above, analog circuits keep becoming more difficult to make as the operating voltage (i.e., VDD) scales, but threshold voltage (i.e., Vt) does not.
At this point it should be noted that duty cycle correction is not the only place to use a high precision integrator. They can be used in other applications where the timing of one event needs to match another event. For example, one such application is an analog phase detector where two edges are adjusted with 90 degrees of phase offset between them (e.g., a quadrature phase detector). In this application, as with the duty cycle correction application, new circuit techniques are needed to produce an integrator with small internal error.
In view of the foregoing, it would be desirable to provide an improved differential integrator which overcomes the above-described inadequacies and shortcomings in an efficient and cost effective manner.
According to the present invention, an improved differential integrator and related circuitry is provided. In one exemplary embodiment, the improved differential integrator comprises an integrating gain boosted cascode circuit for receiving an input signal having a first locking time and for generating an output signal having a second locking time, wherein the second locking time being delayed by a predetermined amount from the first locking time.
According to other aspects of this exemplary embodiment of the present invention, the improved differential integrator further comprises a multi-node common-mode feedback circuit that is coupled to the integrating gain boosted cascode circuit. The multi-node common-mode feedback circuit receives at least one bias signal and reduces offset in a desired common-mode of the output signal based thereon.
According to further aspects of this exemplary embodiment of the present invention, the improved differential integrator further comprises a dynamic cascode common-mode feedback circuit that is coupled to the integrating gain boosted cascode circuit and the multi-node common-mode feedback circuit. The dynamic cascode common-mode feedback circuit compares the output signal and a reference voltage and generates the at least one bias signal in response thereto.
According to still further aspects of this exemplary embodiment of the present invention, the improved differential integrator further comprises a nap mode circuit that is coupled to the integrating gain boosted cascode circuit and the multi-node common-mode feedback circuit. The nap mode circuit receives a feedback signal and a nap signal and determines a sleep mode based thereon, wherein a differential charge associated with the output signal and the second locking time is stored during the sleep mode.
According to still further aspects of this exemplary embodiment of the present invention, the improved differential integrator further comprises a level shifter circuit that is coupled to the integrating gain boosted cascode circuit. The level shifter circuit level shifts the output signal so as to generate a level shifted output signal.
According to still further aspects of this exemplary embodiment of the present invention, wherein the integrating gain boosted cascode circuit is a first integrating gain boosted cascode circuit, the improved differential integrator further comprises a second integrating gain boosted cascode circuit that is coupled to an output node of the first integrating gain boosted cascode circuit. The second integrating gain boosted cascode circuit generates a pair of output signals.
According to another exemplary embodiment of the present invention, an integrating gain boosted cascode circuit is provided comprising a gain boosted cascode structure for receiving substantially equal input voltages and for generating a differential voltage to compensate for channel length modulation. The integrating gain boosted cascode circuit also comprises a capacitor compensation circuit, coupled to an output of the gain boosted cascode structure, for generating an output slew rate of the differential voltage which is slower than an input slew rate of the input voltages such that the differential voltage is a time-averaged gain boosted differential voltage.
According to another exemplary embodiment of the present invention, a multi-node common-mode feedback circuit is provided comprising common-mode feedback circuitry for determining a difference between an input voltage and a reference voltage and for adjusting at least one current branch based on the difference. The multi-node common-mode feedback circuit also comprises at least one current source, coupled to the common-mode feedback circuitry, for receiving at least one current signal via the at least one current branch, wherein a first current branch and a second current branch are adjusted simultaneously to compensate for common-mode correction.
According to another exemplary embodiment of the present invention, a dynamic cascode common-mode feedback circuit is provided comprising common-mode feedback circuitry for receiving an input signal and a reference signal, for determining a difference between the input signal and the reference signal, and for generating a first bias signal for driving a cascoded current source and a second bias signal that varies dynamically with the first bias signal for driving a second current source based upon the difference.
According to another exemplary embodiment of the present invention, a nap mode circuit is provided comprising logic circuitry for receiving a nap signal and a feedback signal and for determining a power save mode based thereon. The nap mode circuit also comprises storage circuitry, coupled to the logic circuitry, for storing a differential charge by disconnecting a differential path during the power save mode, wherein a differential voltage is held constant prior to a wake-up mode to shorten wake-up time.
According to another exemplary embodiment of the present invention, a level shifter circuit for level shifting differential signals is provided comprising first charge storage circuitry for receiving differential signals at an input node. The level shifter circuit also comprises charge pump circuitry, coupled to the first charge storage circuitry, for level shifting the differential signals and for generating level shifted differential signals. The level shifter circuit further comprises second charge storage circuitry, coupled to the charge pump circuitry, for storing the level shifted differential signals and for generating output signals to an output node based thereon. The level shifter circuit further comprises at least one pair of switches coupled to the charge pump circuitry for enabling charge to flow between the input node and the output node so as to establish an equilibrium therebetween.
According to another exemplary embodiment of the present invention, a method for reducing offset in a desired common-mode of a differential integrator is provided comprising the steps of: receiving an input signal having a first locking time; generating an output signal, based upon the input signal, having a second locking time, the second locking time being delayed by a predetermined amount from the first locking time; comparing the output signal and a reference voltage; generating at least one bias voltage signal in response to the comparison; and reducing offset in a desired common-mode based on at least one of the at least one bias voltage signal.
According to another exemplary embodiment of the present invention, a method for generating a time-average gain boosted differential voltage in an integrating gain boosted cascode circuit is provided comprising the steps of: receiving substantially equal input voltages; generating a differential voltage, based upon the input voltages, to compensate for channel length modulation; and generating an output slew rate of the differential voltage which is slower than an input slew rate of the input voltages such that the differential voltage is a time-averaged gain boosted differential voltage.
According to another exemplary embodiment of the present invention, a method for compensating for common-mode correction in a multi-node common-mode feedback circuit is provided comprising the steps of: determining a difference between an input voltage and a reference voltage; adjusting at least one current branch based on the difference; and receiving at least one current signal via the at least one current branch, wherein a first current branch and a second current branch are adjusted simultaneously to compensate for common-mode correction.
According to another exemplary embodiment of the present invention, a method for generating a constant overdrive voltage in a dynamic cascode common-mode feedback circuit is provided comprising the steps of: receiving an input signal and a reference signal; determining a difference between the input signal and the reference signal, and generating a first bias signal for driving a cascoded current source and a second bias signal that varies dynamically with the first bias signal for driving a second current source based upon the difference.
According to another exemplary embodiment of the present invention, a method for implementing a nap circuit is provided comprising the steps of: receiving a nap signal and a feedback signal; determining a power save mode based upon the nap signal and the feedback signal; and storing a differential charge by disconnecting a differential path during the power save mode, wherein a differential voltage is held constant prior to a wake-up mode to shorten wake-up time.
According to another exemplary embodiment of the present invention, a method for level shifting differential signals is provided comprising the steps of: receiving differential signals at an input node; level shifting the differential signals; storing the level shifted differential signals; generating output signals to an output node based upon the stored level shifted differential signals; and enabling charge to flow between the input node and the output node so as to establish an equilibrium therebetween.
The present invention improved differential integrator may be used in different types of circuits such as, for example, duty cycle correctors and charge pumps for phase locked loops. It is particularly useful for low voltage (e.g., less than 2 volts as measured between a transistor gate and source), high precision (e.g., 1% to 2%) applications. Also, some of the aforementioned circuits may be implemented in other circuits such as, for example, the integrating gain boosted cascode circuit, the multi-node common-mode feedback circuit, the dynamic cascode common-mode feedback circuit, the nap mode circuit, and the level shifter circuit.
The present invention will now be described in more detail with reference to exemplary embodiments thereof as shown in the appended drawings. While the present invention is described below with reference to preferred embodiments, it should be understood that the present invention is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present invention as disclosed and claimed herein, and with respect to which the present invention could be of significant utility.